1. Field of the Invention
This invention relates to a semiconductor memory device, and more particularly to a structure of multiple interconnection layers in the memory cell array area of the random access memory (referred to as RAM hereinafter).
2. Description of the Prior Art
In general a semiconductor memory device consists of a memory cell array and peripheral circuits such as decoder circuits and select circuits. Notably in the memory cell array area, there is a number of regularly arranged MOS transistors which memory cells are composed of.
On the other hand, for RAMs, particularly static RAM (SRAM), power line Vcc and ground line GND are required to be disposed between memory cells in the memory cell array area, and thereby the arrangement of MOS transistors is compelled to get out of regularity locally in the vicinity of the connection lines.
MOS transistors which the memory cells are constructed of are multiple interconnection layers each being formed in a regular interconnection pattern in the memory cell array area, and this interconnection pattern is put out of the regularity locally in the vicinity of those connection lines.
The inventors have discovered that variation of dimensions from the design value is greater in such an interconnection layer of locally irregular pattern than in the regular pattern interconnection layer. A dimension of the polycrystalline silicon interconnection layer greater than the design value would result in a greater gate length of MOS transistor (FET) formed on a substrate than the design value, which in turn leads to reduction of the mutual conductance.
The reduction of mutual conductance of the transistor may reflect not only a delayed rising of the digit line potential, lowering of the response speed of the memory device but also cause malfunction.